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data sheet april 2000 l8560 low-power slic with ringing features n full-feature set for central office applications n also ideal for isdn terminal adapters, pair gain, and cable telephony applications n auxiliary input for second battery, and internal switch to enable its use to save power in short tele- phone loops n 5 v only operation or optional 5 v operation for reduced power consumption n low active power (85 mw typical) and scan power (61 mw typical) with 5 v only operation n low active power (68 mw typical with auxiliary bat- tery) and scan power (45 mw typical) with 5 v operation n quiet tip/ring polarity reversal n per-line ringing available for short loops n reduced overhead and increased current limit dur- ing ring mode for lower-battery operation or increased ring loop length n supports meter pulse injection n distortion-free full duplex from 0 ma dc loop cur- rent on-hook transmission n convenient operating states: forward powerup polarity reversal powerup forward sleep ground start disconnect n adjustable supervision functions: off-hook detector with longitudinal rejection ground key detector with longitudinal rejection ring trip detector n independent, adjustable dc and ac parameters: dc feed resistance (44-pin plcc version) loop current limit termination impedance n thermal protection description the l8560 full-feature, low-power subscriber line interface circuit (slic) is optimized for low power consumption while providing an extensive set of fea- tures. this part is ideal for isdn terminal adapter applications and short-loop, power-sensitive applica- tions such as pair gain and cable telephony. this part is also designed for pbx, dlc, or co applications. the slic includes an auxiliary battery input and a battery switch. in short-loop applications, slics can be used in high battery to present a high on-hook voltage, and then switched to low battery to reduce off-hook power. to help minimize the required auxiliary battery volt- age, the dc feed resistance and overhead voltage are set at 55 w and 6.7 v, respectively. this allows an undistorted on-hook transmission of a 3.14 dbm sig- nal into a 900 w loop impedance. the device offers the reverse battery function. using the reverse battery, the device can provide a bal- anced power ring signal to tip and ring. in this mode of operation, the battery switch is used to apply a high-voltage battery during ringing and a lower-voltage battery during the talk and idle states. also included in the l8560 is a dc current-limit switch, which increases the dc current limit during power ringing. in addition, dc overhead voltage is reduced during the ring state. with the battery and current-limit switches, and overhead reduction, the l8560 can provide sufficient power to ring a true north american 5 ren load of 1386 w + 40 m f. the device offers ring trip and loop closure supervi- sion with 0.3 v and 2 ma hysteresis, respectively. it also includes the ground start state and ring ground detection. a summing node for meter pulse injection to 2.2 vrms is also included. the 44-pin plcc ver- sion also has a spare uncommitted op amp, which may be used for ac gain setting or meter pulse filter- ing.
data sheet april 2000 l8560 low-power slic with ringing 2 lucent technologies inc. table of contents contents page features .................................................................... 1 description ................................................................. 1 pin information ........................................................... 6 functional description ................................................ 9 absolute maximum ratings ..................................... 10 recommended operating conditions ...................... 11 electrical characteristics .......................................... 11 ring trip requirements ......................................... 16 test configurations .................................................. 17 applications ............................................................. 19 characteristic curves............................................. 19 dc applications ...................................................... 21 battery feed...................................................... 21 overhead voltage ............................................ 22 adjusting overhead voltage ............................. 23 adjusting dc feed resistance........................... 23 adjusting overhead voltage and dc feed resistance simultaneously.............................. 24 loop range....................................................... 24 off-hook detection ........................................... 24 ring ground detection...................................... 25 longitudinal balance.............................................. 25 power derating ..................................................... 25 battery switch ....................................................... 26 v cc /v ee supplies ................................................... 27 power ringing ....................................................... 27 ringing slic balanced ring signal generation ....................................................... 27 pots for isdn terminal adapters ................... 27 contents page power ringing load .......................................... 28 crest factor....................................................... 28 current-limit switch .......................................... 29 ring trip............................................................ 29 reference designs for isdn ta applications ... 31 design considerations .......................................... 33 unbalanced bused ring signal application ...... 33 ring trip detection............................................ 33 ac design .............................................................. 37 first-generation codecs ................................... 37 second-generation codecs .............................. 37 third-generation codecs .................................. 37 design examples ................................................... 39 example 1, real termination ............................ 39 example 2, complex termination ..................... 39 example 3, complex termination without spare op amp ................................................. 39 complex termination impedance design example using l8560 without spare op amp ............................................................ 40 ac interface using first-generation codec ....... 40 transmit gain.................................................... 41 receive gain..................................................... 42 hybrid balance .................................................. 42 blocking capacitors........................................... 43 outline diagrams...................................................... 44 32-pin plcc ......................................................... 44 44-pin plcc ......................................................... 45 ordering information................................................. 46
data sheet april 2000 lucent technologies inc. 3 l8560 low-power slic with ringing table of contents (continued) figures page figure 1. functional diagram ..................................... 5 figure 2. 32-pin diagram (plcc chip) ...................... 6 figure 3. 44-pin diagram (plcc chip) ...................... 6 figure 4. ring trip circuits....................................... 16 figure 5. basic test circuit ...................................... 17 figure 6. metallic psrr ........................................... 17 figure 7. longitudinal psrr .................................... 17 figure 8. longitudinal balance ................................. 18 figure 9. rfi rejection............................................. 18 figure 10. longitudinal impedance .......................... 18 figure 11. ac gains .................................................. 18 figure 12. l8560 receive gain and hybrid balance vs. frequency .......................... 19 figure 13. l8560 transmit gain and return loss vs. frequency ........................................ 19 figure 14. l8560 typical v cc power supply rejection ................................................ 19 figure 15. l8560 typical v bat power supply rejection ................................................ 19 figure 16. loop closure program resistor selection ................................................ 20 figure 17. ring ground detection programming ..... 20 figure 18. loop current vs. loop voltage................ 20 figure 19. loop current vs. loop resistance .......... 20 figure 20. l8560 typical slic power dissipation vs. loop resistance............................... 21 figure 21. power derating........................................ 21 figure 22. loop current vs. loop voltage................ 21 figure 23. slic 2-wire output stage....................... 23 figure 24. equivalent circuit for adjusting the overhead voltage .................................. 23 figure 25. equivalent circuit for adjusting the dc feed resistance ............................... 23 figure 26. adjusting both overhead voltage and dc feed resistance ............................... 24 figure 27. off-hook detection circuit....................... 24 figure 28. pots controlled from an isdn terminal adapter ................................... 28 figure 29. ringing waveform crest factor = 1.6 ..... 28 figure 30. ringing waveform crest factor = 1.2 ..... 28 figure 31. equivalent ring trip circuit for balanced ringing slic ......................... 29 figure 32. thevenin equivalent ring trip circuit for balanced ringing slic..................... 29 figure 33. pots interface with balanced ringing using l8560 slic and t8503 codec .... 31 figure 34. ring trip equivalent circuit and equivalent application ........................... 33 figure 35. basic loop start application circuit using t7504 codec and bused ringing................................................... 34 figure 36. ground start application circuit .............. 35 figure 37. ac equivalent circuit not including spare op amp ....................................... 38 figure 38. ac equivalent circuit including spare op amp.................................................. 38 figure 39. interface circuit using first-generation codec (blocking capacitors not shown) ................................................... 41 figure 40. ac interface using first-generation codec (including blocking capacitors) for complex termination impedance ..... 43 tables page table 1. l8560 product family feature summary ..... 4 table 2. pin descriptions............................................ 7 table 3. input state coding........................................ 9 table 4. supervision coding ...................................... 9 table 5. power supply ............................................. 12 table 6. 2-wire port ................................................. 13 table 7. analog pin characteristics ......................... 14 table 8. uncommitted op amp characteristics (44-pin plcc only).......... 14 table 9. ac feed characteristics .............................. 15 table 10. logic inputs and outputs.......................... 16 table 11. parts list for balanced ringing using t8503 codec .......................................... 32 table 12. parts list for loop start with bused ringing and ground start applications .. 35 table 13. 600 w design parameters ........................ 37
data sheet april 2000 l8560 low-power slic with ringing 4 lucent technologies inc. description (continued) the l8560 product family is graded by different fea- tures, specifications, and package options. the l8560axx is the basic full-feature slic that operates with 5 v and a battery supply, and is available in the 32-pin plcc (aau) package and the 44-pin plcc package (ap). this part is graded as the 54 db longitu- dinal balance part. additional features (spare op amp and overhead voltage programming) are available in the 44-pin plcc package. the l8560cau is available only in the 32-pin plcc package and has a feature set similar to the aau ver- sion, except the cau version requires +5 v, C5 v, and battery power supplies. with this option, power con- sumption is greatly reduced. the l8560dau and l8560ep are available in the 32-pin and 44-pin plcc packages and have feature sets identical to the l8560aau and l8560ap, respec- tively, with the following modifications. these parts are graded as high longitudinal balance (63 db), and have an additional logic state (scan with low battery) which allows for low on-hook power dissipation. the l8560fau and l8560GP are available in the 32-pin and 44-pin plcc packages and have feature sets identical to the l8560aau and l8560ap, respec- tively, with the following modifications. these parts are graded for lower longitudinal balance (50 db), and have an additional logic state (scan with battery) which allows for low on-hook power dissipation. table 1 below summarizes the features in the l8560 product family. table 1. l8560 product family feature summary * more information is provided in the applications section of this document. feature l8560 aau ap cau dau ep fau gp 32-pin plcc xnax xnaxna 44-pin plcc na x na na x na x 5 v operation x x na x x x x 5 v operation (reduced power consumption) na na x na na na na operational v bat1 (v) C70 C70 C70 C70 C70 C70 C70 battery switch xxxxxxx balanced ring mode x x x x x x x adjustable overhead na x na na x na x spare op amp na x na na x na x reverse battery xxxxxxx scan mode xxxxxxx scan mode with low battery na na na x x x x longitudinal balance (db)* 54 54 54 63 63 50 50 on-hook transmission xxxxxxx ground start x x x x x x x loop start x x x x x x x ring trip detector xxxxxxx programmable current limit x x x x x x x thermal protection x x x x x x x
lucent technologies inc. 5 data sheet april 2000 l8560 low-power slic with ringing description (continued) 12-2569.c (f) figure 1. functional diagram rgdet icm b0 b1 b2 br + C + C ax a = 4 a = C4 power conditioning bgnd bs1 bs2 v cc agnd pt pr dc resistance adjust dcr rtsn rtsp lcth ring trip detector loop closure detector battery feed spare dcout vitr rcvp rcvn xmt sn nstat 1 v tx t xi 0.1 m f 2 rectifier cf2 cf1 battery switch fb1 fb2 tg ring ground detector 44-pin plcc only current-limit adjust i prog 44-pin v bat1 v bat2 internal switch v reg v ee (optional battery enlarged detail v bat2 v bat1 v bat1 decision switch see enlarged detail & reference on l8560c) 19.2 c external op amp + C state control + C + C plcc only
data sheet april 2000 l8560 low-power slic with ringing 6 lucent technologies inc. pin information 12-2548.l (f) figure 2. 32-pin diagram (plcc chip) 12-2548.f (f) figure 3. 44-pin diagram (plcc chip) b0 br b2 pr pt bs1 bs2 icm b1 5 7 8 9 10 11 12 13 14 15 6 432132 30 16 18 19 20 17 31 27 26 25 24 23 22 21 28 29 fb1 fb2 rcvn lcth i prog dcout cf2 cf1 rtsn rcvp txi vtx tg 32-pin plcc rgdet bgnd rtsp vitr agnd nstat v bat2 v bat1 nc (l8560a/d/f) v ee (l8560c) v cc 7 9 10 11 12 13 14 15 16 17 8 6 4 3 2 1 4443424140 5 18 20 21 22 23 24 25 26 dcout nc 27 28 19 39 37 36 35 34 33 32 31 30 29 38 rcvp nc vitr txi vtx tg nc nc-ntp agnd nc rtsp v bat1 bgnd rgdet cf2 bs2 b0 b1 b2 nc pr nc bs1 pt nc fb2 fb1 lcth dcr cf1 sn nc xmt br rcvn nstat nc icm rtsn 44-pin plcc i prog v bat2 v cc
lucent technologies inc. 7 data sheet april 2000 l8560 low-power slic with ringing pin information (continued) table 2. pin descriptions 32-pin 44-pin symbol type description 9 1 dcout o dc output voltage. this output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. 10 2 i prog i current-limit program input. a resistor to dcout sets the dc current limit of the device. 11 3 cf2 filter capacitor 2. connect a 0.1 m f capacitor from this pin to agnd. 12 4 cf1 filter capacitor 1. connect a 0.47 m f capacitor from this pin to pin cf2. 5 sn i summing node. the inverting input of the uncommitted operational amplifier. a resistor or network to xmt sets the gain (44-pin plcc only). 6 xmt o transmit ac output voltage. the output of the uncommitted operational amplifier (44-pin plcc only). 13 7 rtsn i ring trip sense negative. connect this pin to the ringing generator signal through a high-value resistor. 14 8 rtsp i ring trip sense positive. connect this pin to the ring relay and the ringer series resistor through a high-value resistor. 9 nc no connection. may be used as a tie point. 15 10 agnd analog signal ground. 11 nc no connection. may be used as a tie point. 16 12 v cc 5 v power supply. 17 13 v bat1 battery supply. negative high-voltage battery, higher in magnitude than v bat2 . 18 14 v bat2 auxiliary battery supply. negative high-voltage battery, lower in magnitude than v bat1 , used to reduce power dissipation on short loops. 19 15 bgnd battery ground. ground return for the battery supply. 20 16 rgdet o ring ground detect. when high, this open-collector output indicates the pres- ence of a ring ground. to use, connect a 100 k w resistor to v cc . 21 17 icm i common-mode current sense. to program ring ground sense threshold, connect a resistor to v cc and connect a capacitor to agnd to filter 50/60 hz. if unused, the pin should be connected to ground. 22 18 bs2 battery switch slowdown. connect a 0.22 m f capacitor to pin bs1. 23 19 bs1 battery switch slowdown. connect a 0.22 m f capacitor to pin bs2. also, con- nect a 0.1 f capacitor in series with a 100 w resistor from bs1 to v bat1 for sta- bility. 20 nc no connection. may be used as a tie point. 21 nc no connection. may be used as a tie point. 24 22 pt i/o protected tip. the output of the tip driver amplifier and input to loop sensing. connect to loop through overvoltage protection. 25 23 pr i/o protected ring. the output of the ring driver amplifier and input to loop sens- ing circuitry. connect to loop through overvoltage protection.
data sheet april 2000 l8560 low-power slic with ringing 8 lucent technologies inc. pin information (continued) table 2. pin descriptions (continued) 32-pin 44-pin symbol type description 24 nc no connection. may be used as a tie point. 26 25 b2 i state control input. b0, b1, b2, and br determine the state of the slic. see table 3. pin b2 has a 40 k w pull-up. 27 26 b1 i state control input. b0, b1, b2, and br determine the state of the slic. see table 3. pin b1 has a 40 k w pull-up. 28 27 b0 i state control input. b0, b1, b2, and br determine the state of the slic. see table 3. pin b0 has a 40 k w pull-up. 29 28 br i state control input. b0, b1, b2, and br determine the state of the slic. see table 3. pin br has a 40 k w pull-up. 29 nc no connection. may be used as a tie point. 30 nc-ntp no connection. may not be used as a tie point. 31 nc no connection. may be used as a tie point. 30 32 tg transmit gain. connect a 4.32 k w resistor from this pin to vtx. 31 33 vtx o the voltage at this pin is directly proportional to the differential tip/ring current. 32 34 txi ac/dc separation. connect a 0.1 m f capacitor from this pin to vtx . 1 35 nstat o loop detector output/ring trip detector output. this output is a wired- or of the nlc/nrdet outputs. when low, this logic output indicates that an off-hook condition exists or that ringing has been tripped. 2 v ee C5 v power supply l8560c. 2 nc no connection l8560a/d/f. may be used as a tie point. 36 nc no connection. may be used as a tie point. 3 37 vitr o ac output voltage. this output is a voltage that is directly proportional to the differential ac tip/ring current. 4 38 rcvp i receive ac signal input (noninverting). this high-impedance input con- trols the ac differential voltage on tip and ring. 5 39 rcvn i receive ac signal input (inverting). this high-impedance input controls the ac differential voltage on tip and ring. 40 nc no connection. may be used as a tie point. 6 41 fb2 polarity reversal slowdown. connect a capacitor to ground. 7 42 fb1 polarity reversal slowdown. connect a capacitor to ground. 8 43 lcth i loop closure threshold input. connect a resistor to dcout to set off- hook threshold. 44 dcr i dc resistance. short to analog ground for dc feed resistance of 55 w . the dc feed resistance can be increased to a nominal 760 w by shorting dcr to dcout. intermediate values can be set by a simple resistor divider from dcout to ground with the trip at dcr (44-pin plcc only).
lucent technologies inc. 9 data sheet april 2000 l8560 low-power slic with ringing functional description table 3. input state coding table 4. supervision coding b0 b1 b2 br state/definition 1 1 0 1 powerup, forward battery v bat2 . pin pt is positive with respect to pin pr. v bat2 is applied to the tip/ring drive amplifiers. on-hook transmission capability. all supervision activean off-hook condition or a ring trip causes output nstat to go low. 1 0 0 1 powerup, reverse battery v bat2 . pin pr is positive with respect to pin pt. v bat2 is applied to the tip/ring drive amplifiers. on-hook transmission capability. all supervision activean off-hook condition or a ring trip causes output nstat to go low. 1 1 1 1 powerup, forward battery v bat1 . pin pt is positive with respect to pin pr. v bat1 is applied to the tip/ring drive amplifiers. on-hook transmission capability. all supervision activean off-hook condition or a ring trip causes output nstat to go low. 1 0 1 1 powerup, reverse battery v bat1 . pin pr is positive with respect to pin pt. v bat1 is applied to the tip/ring drive amplifiers. on-hook transmission capability. all supervision activean off-hook condition or a ring trip causes output nstat to go low. 0 1 1 1 ground start. tip drive amplifier is turned off. the device presents a high impedance (>100 k w ) to pin pt and a current-limited battery (v bat1 ) to pin pr. output pin rgdet indi- cates current flowing in the ring lead. 0 0 1 1 low-power scan. except for off-hook supervision, all circuits are shut down to conserve power. only the off-hook detector affects output pin nstat. v bat1 is applied to the tip/ring drive amplifiers. pin pt is positive with respect to pin pr. on-hook transmission is disabled. 0 1 0 1 low-power scan (l8560d/e/f/g only). except for off-hook supervision, all circuits are shut down to conserve power. only the off-hook detector affects output pin nstat. v bat2 is ap- plied to the tip/ring drive amplifiers. pin pt is positive with respect to pin pr. on-hook trans- mission is disabled. 0 0 0 1 forward disconnect. the tip and ring amplifiers are turned off and the slic goes into a high-impedance state (>100 k w ). v bat2 is applied to the slic. 1 1/0 1 0 ring state. slic is powered up. v bat1 is applied to the tip and ring amplifiers. current limit is increased by a factor of 2.8. overhead voltage is reduced to approximately 2.4 v. these conditions are necessary to supply sufficient power to drive a true north american 5 ren ringing load (1386 w + 40 m f). loop closure detector is disabledonly the ring trip detector affects output pin nstat. to apply a balanced ring signal to pins pr and pt, apply a 0 v to 5 v square wave to input pin b1. ringing frequency is the frequency of the input wave at b1. to shape the ring signal at pins pr and pt, connect a capacitor from pin fb1 to ground and from pin fb2 to ground. pin nstat pin rgdet 0 = off-hook or ring trip 1 = ring ground 1 = on-hook and no ring trip 0 = no ring ground
data sheet april 2000 l8560 low-power slic with ringing 10 lucent technologies inc. absolute maximum ratings (t a = 25 c) stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. note: the ic can be damaged unless all ground connections are applied before, and removed after, all other connections. furtherm ore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. some of the known examples of conditions that cause such potentials during powerup are 1) an inductor connected to tip and ring can force an overvoltage on v bat through the protection devices if the v bat connection chatters, and 2) inductance in the v bat lead could resonate with the v bat filter capacitor to cause a destructive overvoltage. parameter symbol value unit 5 v power supply v cc 7.0 v C5 v power supply (l8560c) v ee C7.0 v battery (talking) supplies v bat1, v bat2 C75 v v bat2 magnitude iv bat2 i iv bat1 i + 0.4 v logic input voltage C0.5 to +7.0 v analog input voltage C7.0 to +7.0 v maximum junction temperature t j 165 c storage temperature range t stg C40 to +125 c relative humidity range r h 5 to 95 % ground potential difference (bgnd to agnd) 3 v pt or pr fault voltage (dc) v pt , v pr (v bat1 C 5) to +3 v pt or pr fault voltage (10 x 1000 m s) v pt , v pr (v bat1 C 15) to +15 v current into ring trip inputs i rtsp , i rtsn 240 m a
lucent technologies inc. 11 data sheet april 2000 l8560 low-power slic with ringing recommended operating conditions electrical characteristics minimum and maximum values are testing requirements in the temperature range of 25 c to 85 c and battery range of C24 v to C70 v. these minimum and maximum values are guaranteed to C40 c based on component simulations and design verification of samples, but devices are not tested to C40 c in production. the test circuit shown in figure 5 is used, unless otherwise noted. positive currents flow into the device. typical values are characteristics of the device design at 25 c based on engineering evaluations and are not part of the test requirements. supply values used for typical characterization are v cc = 5.0 v, v ee = C5.0 v, v bat1 = C48 v, v bat2 = C25.5 v, unless otherwise noted. parameter min typ max unit ambient temperature C40 85 c loop closure threshold-detection programming range 5 10 i lim ma dc loop current-limit programming range 5 40 50 ma on- and off-hook 2-wire signal level (@ z loop = 200 w ) 2.2 vrms ac termination impedance programming range 150 600 1300 w v bat1 C24 C48 C70 v v bat2 C16 v bat1 v v cc 4.5 5.0 5.5 v v ee (l8560c) C4.75 C5.0 C5.5 v dc feed resistance programming range (excl. rp) 55 55 760 w
data sheet april 2000 l8560 low-power slic with ringing 12 lucent technologies inc. electrical characteristics (continued) table 5. power supply v cc = 5.0 v, v ee = C5.0 v, v bat1 = C48 v, v bat2 = C19 v, unless otherwise noted. 1. this parameter is not tested in production. it is guaranteed by design and device characterization. 2. v ee used for l8560c version only. parameter min typ max unit power supply rejection 500 hz to 3 khz (see figures 6, 7, 14, and 15.) 1 : v cc (1 khz), v ee (1 khz) 2 v bat1, v bat2 (500 hz3 khz) 35 45 db db thermal protection shutdown (t jc ) 165 c thermal resistance, junction to ambient ( q ja ), still air, 44-pin plcc thermal resistance, junction to ambient ( q ja ), still air, 32-pin plcc 47 60 c/w c/w power supplypowerup, no loop current, v bat2 applied l8560a/d/e/f/g: i cc i bat1 i bat2 6.0 120 2.6 7.2 200 3.2 ma a ma power supplypowerup, no loop current, v bat1 applied: i cc (l8560a/d/e/f/g) i bat1 (l8560a) i bat1 (l8560d/e/f/g) i bat2 (l8560d/e/f/g) 6.0 2.8 1.65 1.0 7.2 3.3 2.0 1.3 ma ma ma ma power supplyscan mode, forward battery, no loop current, v bat1 applied: i cc (l8560a/d/e/f/g) i bat1 (l8560a) i bat1 (l8560d/e/f/g) i bat2 (l8560d/e/f/g) 4.0 1.3 0.5 0.9 5.2 1.6 0.75 1.2 ma ma ma ma power supplyscan mode, forward battery, no loop current, v bat2 applied: i cc i bat1 (v bat1 = C65 v) i bat2 (v bat2 = C30 v) 4.1 200 1.2 ma a ma power supplypowerup, no loop current, l8560c only: i cc i ee i bat1 (v bat1 applied) i bat2 (v bat2 applied) i bat1 (v bat2 applied) 5.8 0.9 1.65 1.50 120 7.2 1.26 2.2 1.96 200 ma ma ma ma a power supplyscan, forward battery, no loop current, v bat1 applied, l8560c only: i cc i ee i bat (v bat1 applied) 4.1 0.81 0.43 5.5 1.1 0.56 ma ma ma power supplyring mode, no loop current: i cc i bat1 6.45 2.2 ma ma
lucent technologies inc. 13 data sheet april 2000 l8560 low-power slic with ringing electrical characteristics (continued) table 6. 2-wire port 1. the longitudinal current is independent of dc loop current. 2. current-limit i lim is programmed by a resistor, r prog , from pin i prog to dcout. i lim is specified at the loop resistance where current limiting begins (see figure 22). select r prog (k w ) = 0.616 x i lim (ma) C onset of current limit with input br high. when input br is low, the current will be increased by a factor of 2.8. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. 4. specification is reduced to |v bat1 + 10.5 v| minimum when v bat1 = C70 v at 85 c. 5. ieee is a registered trademark of the institute of electrical and electronics engineers, inc. 6. longitudinal balance of circuit card will depend on loop series protection resistor matching and magnitude. 7. tested at 1000 hz only. full frequency specifications guaranteed by design and device characterization. parameter min typ max unit tip or ring drive current = dc + longitudinal + signal currents 65 ma signal current 15 marms longitudinal current capability per wire 1 8.5 15 marms dc loop current limit 2 : programmability range 3 accuracy (b0 = br = 5 v, r loop = 100 w, v bat1 = C48 v or v bat2 = C25.5 v active) 5 50 5 ma % powerup open loop voltage levels: differential voltage C v bat2 (v bat2 = C25.5 v) differential voltage C v bat1 (v bat1 = C48 v) 4 differential voltage C v bat1 (ring mode) |v bat2 + 6.9| |v bat1 + 7.1| |v bat1 + 5.5| |v bat2 + 6.5| |v bat1 + 6.7| |v bat1 + 2.4| |v bat2 + 6.1| |v bat1 + 6.3| v v v ground start state: pt resistance 100 k w dc feed resistance (for i loop below current limit) 55 80 w loop resistance range (3.17 dbm overload into 600 w ; not in- cluding protection): i loop = 20 ma at v bat1 = C48 v i loop = 20 ma at v bat2 = C24 v 1940 760 w w longitudinal to metallic balance ieee 5 std. 455 (see figure 8.) 6, 7 : l8560a/c: 200 hz to 2999 hz forward/reverse battery 3000 hz to 3400 hz forward/reverse battery l8560d/e: 200 hz to 2999 hz forward battery 3000 hz to 3400 hz forward battery 200 hz to 2999 hz reverse battery 3000 hz to 3400 hz reverse battery l8560f/g: 200 hz to 2999 hz forward/reverse battery 3000 hz to 3400 hz forward/reverse battery 54 49 63 58 58 54 50 45 59 54 68 63 63 59 55 50 db db db db db db db db metallic to longitudinal balance: 200 hz to 4 khz 46 db rfi rejection (see figure 9.) 3 : 0.5 vrms, 50 w source, 30% am mod. 1 khz 500 khz to 100 mhz C55 C45 dbv
data sheet april 2000 l8560 low-power slic with ringing 14 lucent technologies inc. electrical characteristics (continued) table 7. analog pin characteristics 1. loop closure threshold is programmed by resistor r lcth from pin lcth to pin dcout. 2. ring ground threshold is programmed by resistor r icm2 from pin icm to v cc . 3. this parameter is not tested in production. it is guaranteed by design and device characterization. 4. i n is the sourcing current at rtsn. guaranteed if i n is within 5 m a to 30 m a. table 8. uncommitted op amp characteristics (44-pin plcc only) parameter min typ max unit differential pt/pr current sense (dcout): gain (pt/pr to dcout) offset voltage @ i loop = 0 C200 C41.7 200 v/a mv loop closure detector threshold 1 : programming accuracy at 10 ma 20 % ring ground detector threshold 2 : r icm = 83 k w programming accuracy 3 6 10 25 k w % ring trip comparator: input offset voltage 3 internal voltage source (l8560a/d/e/f) internal voltage source (l8560c) current at input rtsp 4 C8.6 C6.1 i n C 0.5 10 C8.2 C5.7 i n C7.6 C5.1 i n + 0.5 mv v v m a rcvn, rcvp: input bias current C0.2 C1 m a loop closure detector hysteresis variation 2 15 ma % thd 3 at v pt/pr = 2.2 vrms, v oh = 12 v, z t = 200 w C35 db vitr output impedance 5 w vitr output offset voltage 20 mv average/dc current to fb1 and fb2 tested as: (|fb1 (fb) (C5 v)| + |fb1 (fb) (C63 v)| + 2|fb1 (fb) (C35 v)| + |fb2 (fb) (C5 v)| + |fb2 (fb) (C63 v)| + 2|fb2 (fb) (C35 v)| + |fb1 (rb) (C5 v)| + |fb1 (rb) (C63 v)| + 2|fb1 (rb) (C35 v)| + |fb2 (rb) (C5 v)| + |fb2 (rb) (C63 v)| + 2|fb2 (rb) (C35 v)|)/16 29 m a accuracy 8 % parameter min typ max unit input offset voltage input offset current input bias current differential input resistance 5 10 200 1.5 mv na na m w output voltage swing (r l = 10 k w ) output resistance (a vcl = 1) 3.5 2.0 vpk w small-signal gbw 700 khz
lucent technologies inc. 15 data sheet april 2000 l8560 low-power slic with ringing electrical characteristics (continued) table 9. ac feed characteristics 1. set by external components. any complex impedance r 1 + r2 || c between 150 w and 1300 w can be synthesized. 2. this parameter is not tested in production. it is guaranteed by design and device characterization. 3. return loss and transhybrid loss are functions of device gain accuracies and the external hybrid circuit. guaranteed performa nce assumes 1% tolerance external components. not tested in production. parameter min typ max unit ac termination impedance 1 150 1300 w longitudinal impedance 0 w total harmonic distortion200 hz to 4 khz 2 : off-hook on-hook 0.3 1.0 % % transmit gain, f = 1 khz (pt/pr to vitr; see figure 11.) C392 C400 C408 v/a receive + gain, f = 1 khz (rcvp to pt/pr) receive C gain, f = 1 khz (rcvn to pt/pr) 7.76 C7.76 8.00 C8.00 8.24 C8.24 group delay 2 : transmit, powerup receive 1 0.5 m s m s gain vs. frequency (transmit and receive) (600 w termination; reference 1 khz, 1 vrms) 2 : 200 hz to 300 hz 300 hz to 3.4 khz 3.4 khz to 16 khz 16 khz to 266 khz C1.00 C0.3 C3.0 0.0 0.0 C0.1 0.05 0.05 0.3 2.5 db db db db gain vs. level (transmit and receive)(reference 0 dbv) 2 : C55 db to +3 db C0.05 0 0.05 db return loss 2, 3 : 200 hz to 500 hz 500 hz to 3400 hz 30 36 db db 2-wire idle-channel noise (600 w termination): psophometric 2 c-message 3 khz flat 2 C87 2 10 C77 12 20 dbmp dbrnc dbrn 4-wire idle-channel noise: psophometric 2 c-message 3 khz flat 2 C82 7 15 C77 12 20 dbmp dbrnc dbrn transhybrid loss 3 : 200 hz to 500 hz 500 hz to 3400 hz 30 36 db db
data sheet april 2000 l8560 low-power slic with ringing 16 lucent technologies inc. electrical characteristics (continued) table 10. logic inputs and outputs parameter symbol min typ max unit input voltages: low level (permissible range) high level (permissible range) v il v ih C0.5 2.0 0.4 2.4 0.7 v cc v v input currents: low level (v cc = 5.25 v, v i = 0.4 v) high level (v cc = 5.25 v, v i = 2.4 v) i il i ih C75 C40 C115 C60 C300 C100 m a m a output voltages (open collector with internal pull-up resistor): low level (v cc = 4.75 v, i ol = 360 m a) high level (v cc = 4.75 v, i oh = C20 m a) v ol v oh 0 2.4 0.2 0.4 v cc v v ring trip requirements n ringing signal: voltage, minimum 35 vrms, maximum 100 vrms. frequency, 17 hz to 23 hz. crest factor, 1.4 to 2. n ringing trip: 100 ms (typical), 250 ms (v bat = C33 v, loop length = 530 w ). n pretrip: the circuits in figure 4 will not cause ringing trip. 12-2572.e (f) figure 4. ring trip circuits ring ring ring 100 w 10 k w 6 m f per ta 909 tip tip tip 2 m f 200 w switch closes < 12 ms 8 m f per tr 57
data sheet april 2000 lucent technologies inc. 17 l8560 low-power slic with ringing test configurations 12-2570.f (f) figure 5. basic test circuit v cc v cc agnd 0.1 m f bs1 20 k w 20 k w nstat rgdet xmt 66.5 k w 13.7 k w rcv 30.9 k w v bat1 v bat1 bgnd pt pr i prog dcout lcth rtsp rtsn icm r loop 23.7 k w 8.25 k w 100 w 100 w v bat2 l8560 slic vtx txi fb2 fb1 0.1 m f bs2 b0 b2 br tg v bat2 0.1 m f b1 tip ring vitr sn xmt rcvn rcvp 4.32 k w 100 w 2 m w 2 m w 274 k w v bat 402 k w 100 w 100 w 100 w 0.1 m f vitr rcv 30.9 k w 66.5 13.7 k w k w for 44-pin plcc for 32-pin plcc 12-2582.b (f) figure 6. metallic psrr 12-2583.b (f) figure 7. longitudinal psrr v s 4.7 m f 100 w v bat or v cc disconnect v t/r v bat or v cc tip ring basic test circuit + C psrr = 20log v s v t/r 900 w bypass capacitor v s 4.7 m f 100 w v bat or v cc disconnect bypass capacitor 56.3 w v bat or v cc tip ring basic test circuit psrr = 20log v s v m 67.5 w 10 m f 10 m f 67.5 w v m + C
data sheet april 2000 l8560 low-power slic with ringing 18 lucent technologies inc. test configurations (continued) 12-2584.c (f) figure 8. longitudinal balance 5-6756.a (f) * hp is a registered trademark of hewlett-packard company. notes: v s = 0.5 vrms 30% am 1 khz modulation. f = 500 khz1 mhz. device in powerup mode 600 w termination. figure 9. rfi rejection 12-2585.a (f) figure 10. longitudinal impedance 12-2587.d (f) figure 11. ac gains tip ring basic test circuit longitudinal balance = 20 log v s v m 368 w 100 m f 100 m f 368 w v m + C v s basic test circuit tip ring v bat 0.01 m f 0.01 m f 600 w 2.15 m f 82.5 w 82.5 w hp * 4935a tims 50 w 1 2 4 6, 7 l7590 v s tip ring basic test circuit + C + C i long i long v pt v pr z long = or d v pt d i long d v pr d i long tip ring basic test circuit 600 w v t/r + C g xmt = v xmt v t/r g rcv = v t/r v rcv xmt (44-pin plcc) rcv v s vitr (32-pin plcc)
data sheet april 2000 lucent technologies inc. 19 l8560 low-power slic with ringing applications characteristic curves 12-2828.c (f) figure 12. l8560 receive gain and hybrid balance vs. frequency 12-2829.b (f) figure 13. l8560 transmit gain and return loss vs. frequency 12-2830.a (f) figure 14. l8560 typical v cc power supply rejection 12-2871.a (f) figure 15. l8560 typical v bat power supply rejection frequency (hz) 100 C20 C10 0 10 4 C50 C40 C30 1000 hybrid balance (db) receive gain 10 5 100 1000 10 4 C50 C30 C20 C10 0 frequency (hz) C40 transmit gain return loss (db) 10 5 10 100 10 6 C80 C70 C20 C10 0 frequency (hz) 1000 C50 C40 C60 C30 psrr (db) current limit below current limit 10 5 10 4 spec. range 10 100 10 5 10 6 C80 C70 C20 C10 0 frequency (hz) 1000 10 4 C50 C40 C60 C30 psrr (db) below current limit current limit spec. range
data sheet april 2000 l8560 low-power slic with ringing 20 lucent technologies inc. applications (continued) characteristic curves (continued) 12-3015 (f) note: v bat1 = C48 v, i tr = 1.2 x 10 C3 r lcth (k w ). figure 16. loop closure program resistor selection 12-3016.f (f) note: tip lead is open; v bat1 = C48 v. figure 17. ring ground detection programming 12-3050.k (f) note: v bat1 = C48 v; i lim = 22 ma; r dc1 = 55 w . figure 18. loop current vs. loop voltage 12-3051 (f) note: v bat1 = C48 v; i lim = 22 ma; r dc1 = 55 w . figure 19. loop current vs. loop resistance 0 5 20 25 0 102030 60 loop closure threshold resistor, r lcth (k w ) 50 15 10 40 off-hook threshold loop current (ma) 0 5 20 35 0 20 40 60 140 100 15 10 80 25 30 120 ring ground current detection resistor, r icm (k w ) threshold ring ground current (ma) 01020 50 0 20 30 40 50 loop voltage (v) 30 40 10 loop current (ma) 1 12.5 k w C1 r dc1 i lim tested i lim onset loop resistance, r loop ( w ) 0 500 1000 2000 0 20 30 40 50 1500 10 loop current (ma)
lucent technologies inc. 21 data sheet april 2000 l8560 low-power slic with ringing applications (continued) characteristic curves (continued) 12-3052 (f) note: v bat1 = C48 v; i lim = 22 ma; r dc1 = 55 w . figure 20. l8560 typical slic power dissipation vs. loop resistance 12-2825.e (f) figure 21. power derating dc applications battery feed the dc feed characteristic can be described by: where: i l = dc loop current. v t/r = dc loop voltage. |v bat | = battery voltage magnitude. note: the l8560 has a battery switch circuit that allows use of a primary battery, v bat1 , or an aux- iliary battery, v bat2 . |v bat | is the battery, v bat1 or v bat2 , that is active. see the battery switch sec- tion for more information. v oh = overhead voltage. this is the difference between the battery voltage and the open loop tip/ring voltage. r l = loop resistance, not including protection resistors. r p = protection resistor value. r dc = slic internal dc feed resistance. the design begins by drawing the desired dc template. an example is shown in figure 22. 12-3050.k (f) note: v bat1 = C48 v; i lim = 22 ma; r dc1 = 55 w . figure 22. loop current vs. loop voltage loop resistance, r loop ( w ) 0 500 1000 2000 0 1000 1500 1500 500 slic power dissipation (mw) ambient temperature, t a ( c) 20 40 60 140 180 0 500 1000 1500 2000 80 100 120 160 power (mw) still air 300 cu. ft./min. 44-pin plcc 32-pin plcc still air 44-pin plcc 250 750 1250 1750 i l v bat v oh C r l 2r p r dc ++ --------------------------------- - = v t/r v bat v oh C () r l r l 2r p r dc ++ -------------------------------------------- = 01020 50 0 20 30 40 50 loop voltage (v) 30 40 10 loop current (ma) 1 12.5 k w C1 r dc1 i lim tested i lim onset
22 22 lucent technologies inc. data sheet april 2000 l8560 low-power slic with ringing applications (continued) dc applications (continued) starting from the on-hook condition and going through to a short circuit, the curve passes through two regions: region 1: on-hook and low loop currents. in this region, the slope corresponds to the dc resistance of the slic, r dc1 (default is 55 w typical). the open circuit voltage is the battery voltage less the overhead voltage of the device, v oh (default is 6.7 v typical). these values are suitable for most applications but can be adjusted if needed. for more information, see the sections titled adjusting dc feed resistance or adjusting overhead voltage. region 2: current limit. the dc current is limited to a starting value determined by external resistor r prog , an internal current source, and the gain from tip/ring to pin dcout. current limit is set by the equation: i prog x r prog = i lim x b dcout where: i prog = the current from an internal current source r prog = the external resistor used to set the current limit b dcout = the transconductance from tip/ring to dcout, which is nominally 41.67 v/a during nonringing modes, the internal current source is set at 75 m a, thus: i prog x r prog = i lim x b dcout r prog = i lim x b dcout /i prog r prog (k) = i lim (ma) x 0.04167 (v/ma)/75e C3 (ma) r prog (k) = 0.556 x i lim (ma) testing data shows that: r prog (k) = 0.616 x i lim (ma) this equation is a first-order estimation of the loop cur- rent at current-limit range. for more precise loop current at current-limit range, the loop current is also determined by loop length, protec- tion resistance, and battery voltage. it can be shown through calculations as follows: current-limit onset (i lonset ): i lonset (ma) = loop resistance where current-limit onsets (r lonset ): r lonset ( w ) = x 1000 C 2r p C rdc tip/ring voltage where current-limit onsets (v t/ronset ): v t/ronset = tip/ring voltage when loop resistance is r loop (v t/rloop ): v t/rloop (v) = i loop (ma) x r loop ( w )/1000 loop current is now given by: i loop (ma) = i lonset (ma) + (v t/ronset C v t/rloop ) (v)/12.5 (k w ) or i loop (ma) = current limit is not sensitive to temperature variation. overhead voltage in order to drive an on-hook ac signal, the slic must set up the tip and ring voltage to a value less than the bat- tery voltage. the amount that the open loop voltage is decreased relative to the battery is referred to as the overhead voltage and is expressed as: v oh = | v bat | C (v pt C v pr ) without this buffer voltage, amplifier saturation will occur and the signal will be clipped. the l8560 is auto- matically set at the factory to allow undistorted on-hook transmission of a 3.17 dbm signal into a 900 w loop impedance. the drive amplifiers are capable of 4 vrms minimum (v amp ). so, the maximum signal the device can guaran- tee is: v t/r = 4 v for applications where higher signal levels are needed, e.g., periodic pulse metering, the 2-wire port of the slic can be programmed with pin dcr (pin dcr is not available in the 32-pin plcc package). the first step is to determine the amount of overhead voltage needed. the peak voltage at output of tip and ring amplifiers is related to the peak signal voltage by: r prog k () 0.616 --------------------------------- v bat v oh C () v () i lonset ma () ------------------------------------------------- - v bat v oh C () r lonset r lonset 2r p rdc ++ ------------------------------------------------------------------- i lonset ma () v t ronset v () + 12.5 k w () 1r loop w () 12500 k w () + ----------------------------------------------------------------------------------------------------------- - z t/r z t/r 2r p + --------------------------------- ? ?? v amp = v t/r 1 2r p z t/r ----------- + ? ?? l l
lucent technologies inc. 23 data sheet april 2000 l8560 low-power slic with ringing applications (continued) dc applications (continued) 12-2563.c (f) figure 23. slic 2-wire output stage in addition to the required peak signal level, the slic needs about 2 v from each power supply to bias the amplifier circuitry. it can be thought of as an internal saturation voltage. combining the saturation voltage and the peak signal level, the required overhead can be expressed as: x 10 dbm/20 where v sat is the combined internal saturation voltage between the tip/ring amplifiers and v bat (4.0 v typ.). r p ( w ) is the protection resistor value. z t/r ( w ) is the ac loop impedance. example 1, on-hook transmission of a meter pulse: signal level: 2.2 vrms into 200 w 35 w protection resistors i loop = 0 (on-hook transmission of the metering signal) v oh = 4.0 + (2.2) = 8.2 v accounting for v sat tolerance of 0.5 v, a nominal over- head of 8.7 v would ensure transmission of an undis- torted 2.2 v metering signal. adjusting overhead voltage to adjust the open loop 2-wire voltage, pin dcr (44-pin plcc only) is programmed at the midpoint of a resistive divider from ground to either C5 v or v bat . in the case of C5 v, the overhead voltage will be indepen- dent of the battery voltage. figure 24 shows the equiv- alent input circuit to adjust the overhead. 12-2562.b (f) figure 24. equivalent circuit for adjusting the overhead voltage the overhead voltage is programmed by using the fol- lowing equation: v oh = 7.1 C 18.18 v dcr = 7.1 C 18.18 adjusting dc feed resistance the dc feed resistance may be adjusted with the help of figure 25. 12-2560.c (f) figure 25. equivalent circuit for adjusting the dc feed resistance r dc = 55 w + 705 w = 55 w + 705 w C v t/r [z t/r ]v amp + C r p r p + v oh v sat 1 2r p z t/r ----------- + ? ?? v t/r + = l v sat 1 2r p z t/r ----------- + ? ?? 2z t/r 1000 -------------- - + = 1 235 200 ---------------- - + ? ?? 2 dcr r 1 r 2 C5 v 5 C r 1 r 2 r 1 + --------------------- ? ?? ? ?? dcr r 1 r 3 dcout 44-pin plcc d v dcr d v dcout ------------------------- - r 1 r 3 r 1 + --------------------- ? ??
24 24 lucent technologies inc. data sheet april 2000 l8560 low-power slic with ringing applications (continued) dc applications (continued) adjusting overhead voltage and dc feed resistance simultaneously the above paragraphs describe the independent set- ting of the overhead voltage and the dc feed resis- tance. if both need to be set to customized values, combine the two circuits as shown in figure 26. 12-2561.d (f) figure 26. adjusting both overhead voltage and dc feed resistance this is an equivalent circuit for adjusting both the dc feed resistance and overhead voltage together. the adjustments can be made by simple superposition of the overhead and dc feed equations: v oh = 7.1 + 40 r dc = 55 k w + 705 w lower-value resistors can be used; the only disadvan- tage is the power consumption of the external resistors. loop range the equation below can be rearranged to provide the loop range for a required loop current: off-hook detection the loop closure comparator has built-in longitudinal rejection, eliminating the need for an external 60 hz fil- ter. this applies in both powerup and low-power scan states. the loop closure detection threshold is set by resistor r lcth . referring to figure 27, nlc is high in an on-hook condition (i tr = 0, v dcout = 0) and v lcth = 0.05 ma x r lcth . the off-hook comparator goes low when v lcth crosses zero and then goes neg- ative: v lcth = 0.05 ma x r lcth + v dcout = 0.05 x r lcth C 0.04167 v/ma x i tr r ltch (k w ) = 0.833 i tr (ma) testing data shows that: r ltch (k w ) = 0.899 i tr (ma) 12-2553.d (f) figure 27. off-hook detection circuit note that nlc is internally wired-or with the output of the ring trip detector (nrdet). the wired-or, nstat, is a package output pin. note that if nstat is used to directly control logic input b2, connect a 0.01 f capacitor from node lcth to ground for filtering purposes. in this mode of operation, the l8560 will automatically switch to the lower-voltage battery under off-hook conditions. also note that nstat will toggle low with a ring ground in the ground start application. under a ring ground, one-half of the current appears as differential. this total ring ground current is approximately two times the cur- rent limit; thus, the differential current is approximately equal to the current limit, which typically exceeds the loop closure threshold. thus, in the ground start appli- cation, if rgdet trips, nstat will also trip. under this condition, via software, ignore the nstat transition. dcr r 1 r 3 dcout r 2 C5 v r 1 r 3 || r 2 r 1 + r 3 || ---------------------------------- - ? ?? r 1 r 2 r 1 + --------------------- ? ?? r l v bat v oh C i l ---------------------------- 2r p C r dc C = r l itr r p r p ring C + C + dcout r lcth lcth nlc tip C0.04167 v/ma 0.05 ma
lucent technologies inc. 25 data sheet april 2000 l8560 low-power slic with ringing applications (continued) dc applications (continued) ring ground detection pin icm sinks a current proportional to the longitudinal loop current. it is also connected to an internal compar- ator whose output is pin rgdet. in a ground start application where tip is open, the ring ground current is half differential and half common mode. in this case, to set the ring ground current threshold, connect a resis- tor r icm from pin icm to v cc . select the resistor according to the following relation: r icm (k w ) = the above equation is shown graphically in figure 17. it applies for the case of tip open. the more general equation can be used in ground key applications to detect a common-mode current icm: r icm (k w ) = longitudinal balance the slics are graded with different codes to represent different longitudinal balance specifications. the num- bers are guaranteed by testing (figures 5 and 8). how- ever, for specific applications, the longitudinal balance may also be determined by termination impedance, protection resistance, and especially by the mismatch between protection resistors at tip and ring. this can be illustrated by: lb = 20 x log where: lb: longitudinal balance rp: protection resistor value in w zt: magnitude of the termination impedance in w : protection resistor mismatch in w d : slic internal tip/ring sensing mismatch the d can be calculated using the above equation with these exceptions: = 0, zt = 600 w, rp = 100 w , and the longitudinal balance specification on a specific code. now with d available, the equation will predict the actual longitudinal balance for rp, zt, and . be aware that zt may vary with frequency for complex impedance applications. power derating thermal considerations can affect the choice of a 32-pin plcc or a 44-pin plcc package. operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop, and protection resis- tor values will influence the overall thermal perfor- mance. this section shows the relevant design equations and considerations in evaluating the slic thermal performance. first, consider the l8560 slic in a 44-pin plcc pack- age. the still-air thermal resistance is 47 c/w; how- ever, this number implies zero airflow as if the l8560 were totally enclosed in a box. a more realistic number would be 43 c/w. this is an experimental number that represents a thermal impedance with no forced airflow (i.e., from a muffin fan) but from the natural airflow as seen in a typical switch cabinet. the slic will enter the thermal shutdown state at typi- cally 165 c. the thermal shutdown design should ensure that the slic temperature does not reach 165 c under normal operating conditions. assume a maximum ambient operating temperature of 85 c, a maximum current limit of 45 ma, and a maxi- mum battery of C52 v. further, assume a (worst case) minimum dc loop of 100 w and that 100 w protection resistors are used at both tip and ring. 1. t tsd C t ambient(max) = allowed thermal rise. 165 c C 85 c = 80 c 2. allowed thermal rise = package thermal impedance ? slic power dissipation. 80 c = 43 c/w ? slic power dissipation slic power dissipation (p d ) = 1.9 w thus, if the total power dissipated in the slic is less than 1.9 w, it will not enter the thermal shutdown state. total slic power is calculated as: to ta l p d = maximum battery ? maximum current limit + slic quiescent power. for the l8560, slic quiescent power (p q ) is approxi- mated at 0.167 w. thus, to ta l p d = (C52 v ? 45 ma) + 0.167 w to ta l p d = 2.34 w + 0.167 w to ta l p d = 2.507 w v cc 120 i rg ma () ---------------------- v cc 60 icm ma () ---------------------- - 368 rp + () 368 zt rp C + () 3682zt2 C rp [] de + () ------------------------------------------------------------------------------------------ - e e e
26 26 lucent technologies inc. data sheet april 2000 l8560 low-power slic with ringing applications (continued) power derating (continued) the power dissipated in the slic is the total power dis- sipation less the power that is dissipated in the loop. slic p d = total power C loop power loop power = (i lim ) 2 ? (r loop(dc) min + 2r p ) loop power = (45 ma) 2 ? (100 w + 200 w ) loop power = 0.61 w slic power = 2.507 w C 0.61 w slic power = 1.897 w < 1.9 w thus, in this example, the thermal design ensures that the slic will not enter the thermal shutdown state. the next example uses the 32-pin plcc package and demonstrates the technique used to determine the maximum allowed current. in this example, assume a 0 c to 70 c operating range. thus, t tsd C t ambient (max) = allowed thermal rise 165 c C 70 c = 95 c to estimate the open-air thermal impedance, use the 43 c/w parameter from the 44-pin plcc and ratio the lead count. thermal impedance (32-pin plcc) = 48 c/w ? = 59 c/w again: allowed thermal rise = thermal impedance ? slic power dissipation 95 c = 59 c/w ? slic power dissipation slic p d = 1.6 w in this example, again assume the dc loop + 2 ? protec- tion resistors = 300 w , then: (i lim )(v bat max) + p q C (i lim ) 2 (r dc + 2 r p ) = 1.6 w i ? 52 + 0.167 C i 2 300 = 1.6 w 300 i 2 C 52 i + 1.433 = 0 this is a quadratic equation whose solution is in the form: x = i lim = i lim = ignore the + term: i lim = thus, 34 ma is the maximum allowable current limit in the 32-pin plcc package under the conditions given in this example. this type of analysis should be performed under the conditions of the users particular application to ensure adequate thermal design. battery switch the l8560 slic provides an input for an auxiliary bat- tery. called v bat2 , this power supply should be lower in magnitude than the primary battery v bat1 . under an acceptable loop condition, v bat2 can be switched to provide the loop power through the amplifiers of the slic. the dc template, described in previous sections, is determined by the battery that is activeeither v bat1 or v bat2 . there are several important applications where use of a lower-voltage battery in the off-hook state is desired to provide dc current to the loop, yet a higher-voltage battery is desired in on-hook or ringing modes. these applications are typically short-loop applications, such as an isdn terminal adapter, fiber-in-the-loop applica- tions, or a cable telephony interface. typically, in these applications, the maximum dc loop resistance (which includes the off-hook telephone handset plus twisted-cable pair) is relatively low. for example, bellcore ta-909, generic requirements and objectives for fiber in the loop systems , specifies that in the off-hook state, 20 ma must be provided into a 430 w dc loop. to meet these requirements, a lower battery in the off-hook condition is important to mini- mize off-hook power consumption. power conservation is important from a cost of energy point of view and is vital in remotely powered pots interface applications. while use of a low-voltage battery in off-hook short dc loops is important, certain on-hook applications, such as providing a balanced power ring signal or maintain- ing compatibility with certain cpe such as answering machines, may require a higher magnitude battery. with the logic-controlled battery switch, the l8560 is able to provide a higher-voltage battery to meet on- hook battery voltage requirements. at the same time, the l8560 can accept a lower-voltage auxiliary battery during short-loop, off-hook applications. if a dc/dc con- verter with two fixed voltage outputs is used, tie the battery voltage that is higher in magnitude to v bat1 and the voltage that is lower in magnitude to v bat2 . if it is 44 32 ------ - Cb b 2 4ac C 2a ---------------------------------------- 52 52 2 (4)(300)(1.433) C 2(300) -------------------------------------------------------------------------------- 52 31.4 600 ----------------------------- - 52 C 31.4 600 ------------------------ - 34 ma =
lucent technologies inc. 27 data sheet april 2000 l8560 low-power slic with ringing applications (continued) battery switch (continued) desired to use a single battery supply or a dc/dc con- verter with a single programmable voltage output, tie v bat1 to v bat2 and connect the battery to this node. note that v bat1 is forced during the balanced ringing state. v cc /v ee supplies the l8560a/d/e/f slics are designed to operate using battery and only a 5 v power supply. in this mode of operation, power for the tip/ring drive amplifiers, dc feedback loop, internal amplifiers, logic, ac, and refer- ence circuits is drawn from the negative battery (and 5 v supply). while the l8560a/d/e/f type devices offer very low power dissipation in both the sleep and active states, further reduction in power dissipation is possible by use of battery and +5 v and C5 v power supplies. the l8560c operates using battery, +5 v, and C5 v power supplies. when the C5 v is used, the internal amplifi- ers, logic, ac, and reference circuits draw power from the negative C5 v supply, not the negative battery. since the magnitude of the C5 v supply is less than the battery, power consumption is reduced. with the l8560c, the tip/ring drive amplifiers and dc feedback loop still draw power from the battery. power ringing the l8560 ringing slic is designed with the capability of generating balanced power ring signal to tip and ring. because the slic itself generates the power ring- ing signal, no ring relay is needed in this mode of oper- ation. alternatively, the l8560 slic can also be used in the more standard battery-backed, unbalanced ringing application. in this case, the ring signal is generated by a central ring generator and is bused to individual tip/ ring pairs. a ringing relay is used during ringing to dis- connect the slic from, and apply the ring generator to, the tip and ring pair. this section discusses in detail the use of the l8560 ringing slic in either mode of application. ringing slic balanced ring signal generation the internal dc current source drives current into or pulls current out from c fb1 and c fb2 depending on whether the slic is operating at battery forward or at battery reversal. the voltage at pt then will be positive with respect to pr or vice versa. if a square wave sig- nal is added to b1, the slic will be operating consecu- tively at battery forward, and then battery reversal. the differential output at pt and pr can be a balanced power ringing signal. its frequency is equal to that of the square wave at b1. its slew rate is determined by the size of the capacitors c fb1 and c fb2 . if a sinusoidally modulated pulse-width-modulation (pwm) signal is applied to b1, the differential output at pt and pr will be sinusoidal. theoretically, it provides power ringing in a sinusoidal format. for more informa- tion, please refer to the l8560 sinusoidal ringing gen- eration using a pwm input to b1 application note. pots for isdn terminal adapters the l8560 ringing slic is designed to provide a bal- anced power ring signal to tip and ring. this mode of operation is suited for short-loop, plain old telephone service (pots) applications, such as isdn terminal adapters (ta). when isdn was first visualized, it was thought that we would all exchange our existing telephones for new, full-feature isdn phones. digital technology would drive these sets to very low costs. while this may hap- pen in the future, the current demand is for the isdn ta to service a standard analog telephone. the chal- lenges of this application are discussed here along with a suggested solution. until recently, pots has been the exclusive domain of the service provider. over its 100-year history, any architectural change was always required to be com- patible with the existing installed local loop plant and all telephone sets. if this is the expectation of the ta, it would be capable of being connected into the residence phone wiring to drive every phone in the house. it would also be designed with enough backup battery to provide unin- terrupted service during electrical power interruptions. in this case, adherence to a standard, such as bellcores ta-909, is recommended. for the case where a ta is only going to provide limited service, the design can be made less costly by limiting the scope of the device. an example of this limited scope would be the provision of analog jacks for a fax/ modem and a phone set near the ta in a home office environment. a block diagram of a pots design is out- lined in figure 28.
data sheet april 2000 l8560 low-power slic with ringing 28 lucent technologies inc. applications (continued) power ringing (continued) 12-3286 figure 28. pots controlled from an isdn terminal adapter prot. slic ringer codec tdm m p isdn ta to telephone set rj-11 xmt rcv to isdn service rj-45 dx, dr clk, fs dtmf decoder power ringing load bellcore ta-909 specifies that a minimum 40 vrms must be delivered to a 5 ren ringing load of 1380 w + 40 m f. during the ringing state, v bat1 is automatically applied to the tip/ring power amplifiers. for 5 ren load, it is recommended that v bat1 be set to C65 vdc. also during the power ring state, the dc current limit is automatically boosted by a factor of 2.8 over the cur- rent limit set by resistor r prog . both of these factors are necessary to ensure delivery of 40 vrms to the north american 5 ren ringing load of 1380 w + 40 m f. crest factor the balanced trapezoidal ring signal is generated by simply toggling the slic between the powerup state forward and powerup reverse battery states. the state change is done by applying a square wave (whose fre- quency is the desired ring frequency) to logic input b1. capacitors fb1 and fb2 are used to control or ramp the speed of the transition of the battery reverse, thus shaping the balanced ring signal. waveforms of crest factors 1.6 and 1.2 are shown in figure 29 and figure 30. in a real application, the ringing trapezoidal waveform crest factor can be estimated by: crest factor = where: f = ringing frequency; c fb = (c fb1 + c fb2 )/2; i cs = 29 m a @ 8% accuracy over temperature; v oh = slic overhead during ring. 12-3346a (f) note: slew rate = 5.65 v/ms; trise = tfall = 23 ms; pwidth = 2 ms; period = 50 ms. figure 29. ringing waveform crest factor = 1.6 12-3347a (f) note: slew rate = 10.83 v/ms; trise = tfall = 12 ms; pwidth = 13 ms; period = 50 ms. figure 30. ringing waveform crest factor = 1.2 1 1 4f c fb v bat v oh C () 3i cs ---------------------------------------------------------------------------- C ------------------------------------------------------------------------------------------ time (s) C80 C60 C40 C20 0 20 40 60 80 0.00 0.02 0.06 0.04 0.08 0.10 0.12 0.14 0.16 0.18 0.20 volts (v) time (s) C80 C60 C40 C20 0 20 40 60 80 0.00 0.02 0.06 0.04 0.08 0.10 0.12 0.14 0.16 0.18 0.20 volts (v)
lucent technologies inc. 29 data sheet april 2000 l8560 low-power slic with ringing applications (continued) power ringing (continued) current-limit switch during nonringing modes, the internal current source is set at 75 m a. during the ring mode, the current limit is automatically increased by a factor of 2.8. this is done to provide sufficient ring to a true north american 5 ren load. this is done internally by increasing the value of i prog from 75 m a to 210 m a, thus: i prog ? r prog = l lim ? b dcout r prog = l lim ? b dcout /i prog r prog (k) = l lim (ma) ? 0.04167 (v/ma)/210eC3 (ma) r prog (k) = 0.198 ? l lim (ma) in the current-limit region, the dc template has a high resistance (12.5 k w ). ring trip ring trip is accomplished by filtering the voltage seen at node dcout and applying it to the integrated ring trip comparator. dcout is a voltage proportional to the tip/ring current, and under short dc loop conditions, on- hook ringing current and off-hook current provide suffi- cient voltage differential at dcout to distinguish that a ring trip condition has occurred. the ring trip compara- tor threshold is set via a resistor between the ring trip comparator and ground. output nstat is automatically set to detect ring trip during the balanced ring mode. during quiet intervals of ringing, output nstat is automatically determined by the loop closure detector. the equivalent ring trip circuit for the balanced ringing slic application is shown in figure 31. the equations governing ring trip are derived below. capacitors c 2 and c 4 , in conjunction with resistors r 2 and r 4 , form a double-pole, low-pass filter that smooths the voltage seen at dcout. the poles of the filters are determined by c 2 and c 4 . where these poles are set will influence both the ripple seen at dcout and the speed of the transition of the voltage at dcout from the pretrip to the tripped level. for the derivation of the ring trip threshold equations, capaci- tors c 2 and c 4 can be ignored. redrawing the circuit, ignoring the capacitors, and tak- ing the thevenin equivalent circuit of the network at rtsn gives the results shown below in figure 32. 12-3349.b (f) figure 31. equivalent ring trip circuit for balanced ringing slic 12-3348.b (f) figure 32. thevenin equivalent ring trip circuit for balanced ringing slic C + 15 k w 8.2 v i p = i n r 2 nrdet r tsp i n r tsn nstat nlc r 4 r 1 dcout c 2 r 3 c 4 C + 15 k w 8.2 v i p = i n r 2 nrdet r tsp i n r tsn nstat nlc r 4 r 1 r 3 /(r 1 + r 3 ) (r 3 /[r 1 + r 3 ]) dcout
data sheet april 2000 l8560 low-power slic with ringing 30 lucent technologies inc. applications (continued) power ringing (continued) at the trip point, the internal current repeater will force i rtsp to be equal to i rtsn and v rtsp will be equal to v rtsn , which is C8.2 v. thus, at the trip point: thus: solving for v dcout , the voltage at dcout at the ring trip point is given by: the loop current at ring trip is given by: i loop(trip) = (v dcout )/( b dcout ) for the l8560, the gain ( b ) at pin dcout is 41.67 v/a. capacitors c 2 and c 4 , along with resistors r 2 and r 4 , respectively, form low-pass filters to filter the ac voltage seen at dcout before it is applied to the ring trip comparator input. the lower the pole of the filter, the less the ripple, but also the slower the state transition at nstat. poles in the neighborhood of 2.5 hz3 hz are suggested, as given by: f lp = f lp = in the reference designs discussed in the next section, the ring trip threshold is set for 50 ma with: r 1 = 210 k w r 2 = 124 k w c 2 = 0.1 m f r 3 = 562 k w r 4 = 351 k w c 4 = 0.1 m f except for l8560cau, the internal voltage for l8560cau is C5.7 v. 133 k w should be used for r 1 . i rtsn r 3 r 3 r 1 + ------------------ v dcout ? ?? 8.2 v C () C r 1 r 3 r 1 r 3 + ------------------ r 2 15 k w ++ ---------------------------------------------------------------------- = i rtsn i rtsp 08.2 C () C r 4 ------------------------- == r 3 r 3 r 1 + -------------------- - ? ?? v dcout 8.2 v + r 1 r 3 r 1 r 3 + -------------------- -r 2 15 k w ++ ---------------------------------------------------------------------- - 8.2 v r 4 -------------- = v dcout 8.2 r 3 r 1 + () r 1 r 1 r 4 r 3 r 4 + ------------------------------------ r 2 r 3 r 4 -------------- - 15 k w r 3 r 4 ---------------- 1 r 3 ------ - C ++ = ( trip ) 1 2 p r 2 c 2 ----------------------- 1 2 p r 4 c 4 -----------------------
lucent technologies inc. 31 data sheet april 2000 l8560 low-power slic with ringing applications (continued) power ringing (continued) reference designs for isdn ta applications a pots circuit for reference design is shown in figure 33. in figure 33, the l8560 slic and t8503 codec are used. the ac circuit is designed per bellcore ta-909 with a 600 w resistive termination and hybrid circuit, with the transmit gain set for C2 db and the receive gain set for C4 db. the t8503 codec is compatible with the t7237 u-interface transceiver and the t7256 scnt1 interface. 12-3345.r (f) *r 1 = 133 k w for l8560c. ? required only for l8560a/c versions. notes: t x = C2 db. r x = C4 db. termination = 600 w. hybrid balance = 600 w. figure 33. pots interface with balanced ringing using l8560 slic and t8503 codec gsx vfrop dx dr fsx mclk sync tip r pt ring pt bs1 bs2 bgnd agnd vitr rcvp tg vtx tx1 c b2 vfxin c f1 cf1 cf2 pr b0 b1 b2 fgnd v bat control r 1 (rts2)* r lcth c 2 dgnd agnd v dd 1 2 4 6, 7 16 pcm r 2 r 4 c fb1 c bs c bat2 c bat1 fb1 v cc v bat1 v bat2 br r pr r 3 r tg dgnd cv dd rcvn c st fsr c tg r st 210 k w 8.25 k w (rts3) 562 k w (rtsn) 0.1 m f (rtsn) 124 k w c 4 (crtsp) 0.1 m f supervision output rgdet ntstat icm rtsp rtsn lcth dcout i prog r prog 14 k w inputs 30 w l7591 30 w 0.1 m f 0.1 m f 0.1 m f 100 w 0.22 m f 4.7 nf c fb2 4.7 nf c f2 0.1 m f fb2 0.47 m f 0.1 m f 27 pf ? 4.32 k w r gn 30.1 k w r gp 41.2 k w r gp2 1.21 k w r rcv 178 k w c c2 0.1 m f c c1 0.1 m f r t6 60.4 k w r hb1 143 k w highway and clock 0.1 m f 1/2 t8503 codec (rtsp) 351 k w c cc 0.1 m f c gp 220 pf r x 71.5 k w r t3 165 k w l8560a, d, e, f, g
data sheet april 2000 l8560 low-power slic with ringing 32 lucent technologies inc. applications (continued) power ringing (continued) table 11. parts list for balanced ringing using t8503 codec * required for l8560a/l8560c version only. ? use 133 k w for l8560c. name value function integrated circuits slic l8560 subscriber line interface circuit (slic). protector l7591 secondary protection. codec t8503 first-generation codec. fault protection r pt 30 w fusible overcurrent protection. r pr 30 w fusible overcurrent protection. power supply c bat1 0.1 m f, 20%, 100 v v bat filter capacitor. c bat2 0.1 m f, 20%, 100 v v bat filter capacitor. c cc 0.1 m f, 20%, 10 v v cc filter capacitor. c f1 0.47 m f, 20%, 100 v with c f2 , improves idle-channel noise. c f2 0.1 m f, 20%, 100 v with c f1 , improves idle-channel noise. c bs 0.22 m f, 20%, 100 v slows battery switch transition. c st 0.1 m f, 20%, 10 v loop stability. r st 100 w , 1%, 1/8 w loop stability. dc profile/ringing c fb1 4.7 nf, 20%, 100 v with c fb2 , slows rate of forward/reverse battery transition. sets crest factor of balanced power ring signal. c fb2 4.7 nf, 20%, 100 v with c fb1 , slows rate of forward/reverse battery transition. sets crest factor of balanced power ring signal. r prog 14 k w , 1%, 1/8 w sets dc loop current. ac characteristics r tg 4.32 k w , 1%, 1/8 w sets internal transmit path gain to 19.2. c b2 0.1 m f, 20%, 10 v ac/dc separation capacitor. c c1 0.1 m f, 20%, 10 v dc blocking capacitor. c c2 0.1 m f, 20%, 10 v dc blocking capacitor. r t3 165 k w , 1%, 1/8 w with r gp and r rcv , sets ac termination impedance. r rcv 178 k w , 1%, 1/8 w with r gp and r t3 , sets receive gain. r gp 41.2 k w , 1%, 1/8 w with r t3 and r rcv , sets ac termination impedance and receive gain. c gp 220 pf, 20%, 10 v loop stability. c tg * 27 pf, 20%, 10 v loop stability. r gp2 1.21 k w , 1%, 1/8 w loop stability. r gn 30.1 k w , 1%, 1/8 w compensates for input bias offset at rcvn/rcvp. r t6 60.4 k w , 1%, 1/8 w with r x , sets transmit gain in codec. r x 71.5 k w , 1%, 1/8 w with r t6 , sets transmit gain in codec. r hb1 143 k w , 1%, 1/8 w sets hybrid balance. supervision r lcth 8.25 k w , 1%, 1/8 w sets loop closure (off-hook) threshold. r 1 (rts2) ? 210 k w , 1%, 1/8 w with r 2 , r 3 , and r 4 , sets ring trip threshold. r 2 (rtsn) 124 k w , 1%, 1/8 w with r 1 , r 3 , and r 4 , sets ring trip threshold. c 2 (crtsn) 0.1 m f, 20%, 50 v with r 2 , sets pole of low-pass ring trip sense filter. r 3 (rts3) 562 k w , 1%, 1/8 w with r 1 , r 2 , and r 4 , sets ring trip threshold. r 4 (rtsp) 351 k w , 1%, 1/8 w with r 1 , r 2 , and r 3 , sets ring trip threshold. c 4 (crtsp) 0.1 m f, 20%, 10 v with r 4 , sets pole of low-pass ring trip sense filter.
lucent technologies inc. 33 data sheet april 2000 l8560 low-power slic with ringing applications (continued) design considerations unbalanced bused ring signal application the l8560 slic can also be used in the standard bat- tery-backed, unbalanced ringing application. in this case, the ring signal is generated by a central ring gen- erator and is bused to individual tip/ring pairs. a ringing relay is used during ringing to disconnect the slic from, and apply the ring generator to, the tip and ring pair. ring trip detection the ring trip circuit is a comparator that has a special input section optimized for this application. the equiva- lent circuit is shown in figure 34, along with its use in an application using unbalanced, battery-backed ringing. 12-3014.c (f) figure 34. ring trip equivalent circuit and equivalent application the comparator input voltage compliance is v cc to v bat , and the maximum current is 240 m a in either direction. its application is straightforward. a resistance (r tsn + r ts2 ) in series with the r tsn input establishes a current that is repeated in the r tsp input. a slightly lower resistance (r tsp ) is placed in series with the r tsp input. when ringing is being injected, no dc current flows through r ts1 , so the r tsp input is at a lower potential than r tsn . when enough dc loop current flows, the r tsp input voltage increases to trip the com- parator. in figure 34, a low-pass filter with a double pole at 2 hz was implemented to prevent false ring trip. the following example illustrates how the detection cir- cuit in figure 34 will trip at a 12.5 ma dc loop current using a C48 v battery. the current i n is repeated as i p in the positive compar- ator input. the voltage at comparator input r tsp is: v rtsp = v bat + i loop(dc) x r ts1 + i p x r tsp using this equation and the values in the example, the voltage at input r tsp is C13.2 v during ringing injection (i loop(dc) = 0). input r tsp is therefore at a level of 5 v below r tsn . when enough dc loop current flows through r ts1 to raise its dc drop to 5 v, the comparator will trip. in this example: i loop(dc) = = 12.5 ma except for l8560cau, the internal voltage for l8560cau is C5.7 v. note that during ringing in this mode of operation, both the nlc and nrdet circuits are active. during the actual ringing, nrdet is connected and nlc is iso- lated from tip and ring by the ring relay; thus, nstat reflects the status at nrdet. during quiet intervals of ringing, nlc is connected and nrdet is isolated from tip and ring by the ring relay; thus, nstat reflects the status at nlc. thus, during ring cadence, the logic input that drives the ring relay can be used as an indi- cation as to whether nrdet or nlc appears at output nstat. a basic loop start reference circuit, using bused ringing with the l8560 slic and t7504 first-generation codec, is shown in figure 35. this circuit is designed for a 600 w resistive termination impedance and hybrid balance. transmit and receive gains are both set at 0 db. + C r tsp r loop 15 k w 8.2 v i p = i n r tsn r ts2 2 m w 2 m w c rts1 0.022 m f c rts2 0.27 m f 274 k w phone hook switch rc phone v ring v bat nrdet r ts1 402 w r tsp i n r tsn C + i n C8.2 v C (C48) 2.289 m w ------------------------------------- - = 17.4 a = 5 v 402 w ---------------- -
data sheet april 2000 l8560 low-power slic with ringing 34 lucent technologies inc. applications (continued) design considerations (continued) 12-3550 (f) * required for l8560a/l8560c version only. notes: t x = 0 db. r x = 0 db. termination = 600 w. hybrid balance = 600 w. figure 35. basic loop start application circuit using t7504 codec and bused ringing r prog 14 k w r lcth 8.25 k w tip r pt 50 w ring r pr l7581 relay tip v bat1 c bat1 0.1 m f v bat1 v bat2 c bat2 0.1 m f v bat2 c cc 0.1 m f v cc v cc rcvn dcout lcth 50 w ring rtsp r ts1 402 w c rts2 0.27 m f rtsn r ts2 274 k w r tsn 2.0 m w v ring v bat cf2 cf1 c f1 0.47 m f agnd bgnd i prog vitr rcvp r t3 174 k w r t6 49.9 k w r rcv 100 k w r hb1 75.0 k w vfxin r x 75.0 k w gsx v fro dx dr fse fsep mclk asel 1/4 t7504 codec control inputs pcm highway sync and clock C + l8560 slic b1 b0 control inputs nstat supervision outputs c rts1 0.022 m f txi v tx c b2 0.1 m f r tsp 2.0 m w c f2 0.1 m f r gx 4.32 k w tg bs1 bs2 c bs 0.22 m f +2.4 v c c1 0.1 m f c c2 0.1 m f r gn 29.4 k w r gp 41.2 k w 100 w c st 0.1 m f c gp 220 pf r gp2 1.21 k w c tg 27 pf* r st crowbar protector crowbar protector
lucent technologies inc. 35 data sheet april 2000 l8560 low-power slic with ringing applications (continued) design considerations (continued) figure 36 shows the ground start application. 12-3547.a.c (f) figure 36. ground start application circuit table 12. parts list for loop start with bused ringing and ground start applications * contact your lucent technologies account representative for protector recommendations. choice of this (and all) component(s) s hould be evaluated and confirmed by the customer prior to use in any field or laboratory system. lucent does not recommend use of this p art in the field without performance verification by the customer. this device is suggested by lucent for customer evaluation. the decisio n to use a component should be based solely on customer evaluation. ? required for l8560a/l8560c version only. name value function integrated circuits slic subscriber line interface circuit (slic). protector crowbar protector* secondary protection. ringing relay l7581 switches ringing signals. codec t7504 first-generation codec. fault protection r pt 50 w ptc or fusible protection resistor. r pr 50 w ptc or fusible protection resistor. power supply c bat1 0.1 m f, 20%, 100 v v bat filter capacitor. c bat2 0.1 m f, 20%, 100 v v bat filter capacitor. c cc 0.1 m f, 20%, 10 v v cc filter. c f1 0.47 m f, 20%, 100 v with c f2 , improves idle-channel noise. c f2 0.1 m f, 20%, 100 v with c f1 , improves idle-channel noise. c bs 0.22 m f, 20%, 100 v slows battery switch transition. c st 0.1 m f, 20%, 10 v loop stability. r st 100 w , 1%, 1/8 w loop stability. c tg ? 27 pf, 20%, 10 v loop stability. dc profile r prog 14 k w , 1%, 1/8 w sets dc loop current. v cc 0.47 m f c icm ground start application circuit r gdet icm r gdet r icm2 71.5 k w 100 k w r gdet
data sheet april 2000 l8560 low-power slic with ringing 36 lucent technologies inc. applications (continued) design considerations (continued) table 12. parts list for loop start with bused ringing and ground start applications (continued) name value function ac characteristics r gx 4.32 k w , 1%, 1/8 w sets internal transmit path gain of 9.6. c b2 0.1 m f, 20%, 10 v ac/dc separation capacitor. r t3 174 k w , 1%, 1/8 w with r gp and r rcv , sets ac termination impedance. r rcv 100 k w , 1%, 1/8 w with r gp and r t3 , sets receive gain. r gp 41.2 k w , 1%, 1/8 w with r t3 and r rcv , sets ac termination impedance and receive gain. c gp 220 pf, 20%, 10 v loop stability. r gp2 1.21 k w , 1%, 1/8 w loop stability. r gn 29.4 k w , 1%, 1/8 w compensates for input bias offset at rcvn/rcvp. c c1 0.1 m f, 20%, 10 v dc blocking capacitor. c c2 0.1 m f, 20%, 10 v dc blocking capacitor. r t6 49.9 k w , 1%, 1/8 w with r x , sets transmit gain in codec. r x 75.0 k w , 1%, 1/8 w with r t6 , sets transmit gain in codec. r hb1 75.0 k w , 1%, 1/8 w sets hybrid balance. supervision r lcth 8.25 k w , 1%, 1/8 w sets loop closure (off-hook) threshold. r ts1 402 w , 5%, 2 w ringing source series resistor. r ts2 274 k w , 1%, 1/8 w with c rts2 , forms first pole of a double pole, 2 hz ring trip sense filter. c rts1 0.022 m f, 20%, 5 v with r tsn and r tsp , forms second 2 hz filter pole. c rts2 0.27 m f, 20%, 100 v with r ts2 , forms first 2 hz filter pole. r tsn 2 m w , 1%, 1/8 w with c rts1 and r tsp , forms second 2 hz filter pole. r tsp 2 m w , 1%, 1/8 w with c rts1 and r tsn , forms second 2 hz filter pole. ground start c icm 0.47 m f, 20%, 10 v provides 60 hz filtering for ring ground detection. r gdet 100 k w , 20%, 1/8 w digital output pull-up resistor. r icm2 71.5 k w , 1%, 1/8 w sets ring ground detection threshold.
data sheet april 2000 lucent technologies inc. 37 l8560 low-power slic with ringing applications (continued) design considerations (continued) table 13 shows the design parameters of the application circuit shown in figure 35. components that are adjusted to program these values are also shown. table 13. 600 w design parameters design parameter parameter value components adjusted loop closure threshold 10 ma r lcth dc loop current limit 25 ma r prog dc feed resistance 55 w 2-wire signal overload level 3.14 dbm ac termination impedance 600 w r t3 , r gp , r rcv hybrid balance line impedance 600 w r hb1 transmit gain 0 db r t6 , r x receive gain 0 db r rcv , r gp , r t3 ac design there are four key ac design parameters. termination impedance is the impedance looking into the 2-wire port of the line card. it is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. transmit gain is measured from the 2-wire port to the pcm highway, while receive gain is done from the pcm highway to the transmit port. finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. at this point in the design, the codec needs to be selected. the discrete network between the slic and the codec can then be designed. below is a brief codec feature and selection summary. first-generation codecs these perform the basic filtering, a/d (transmit), d/a (receive), and m -law/a-law companding. they all have an op amp in front of the a/d converter for transmit gain setting and hybrid balance (cancellation at the summing node). depending on the type, some have differential analog input stages, differential analog output stages, and m -law/a-law selectability. this generation of codec has the lowest cost. it is most suitable for applications with fixed gains, termination impedance, and hybrid bal- ance. second-generation codecs this class of devices includes a microprocessor inter- face for software control of the gains and hybrid bal- ance. the hybrid balance is included in the device. ac programmability adds application flexibility and saves several passive components. it also adds several i/o latches that are needed in the application. it does not have the transmit op amp, since the transmit gain and hybrid balance are set internally. third-generation codecs this class of devices includes the gains, termination im- pedance, and hybrid balanceall under microproces- sor control. depending on the device, it may or may not include latches. in the codec selection, increasing software control and flexibility are traded for device cost. to help decide, it may be useful to consider the following: will the appli- cation require only one value for each gain and imped- ance? will the board be used in different countries with different requirements? will several versions of the board be built? if so, will one version of the board be most of the production volume? does the application need only real termination impedance? does the hybrid balance need to be adjusted in the field?
data sheet april 2000 l8560 low-power slic with ringing 38 lucent technologies inc. applications (continued) ac design (continued) ac equivalent circuits using a t7504 codec (v cc only) are shown in figures 37 and 38. use the following two equa- tions for figure 37 below: r stp = 1 k w x {[r gp (k w ) || r rcv (k w )]/24 (k w )} c stp = 270 pf/{[r gp (k w ) || r rcv (k w )]/24 (k w )} 12-2554.p (f) figure 37. ac equivalent circuit not including spare op amp use the following two equations for figure 38 below: r stn = 1 k w x {[r gn (k w ) || r rcv (k w )]/24 (k w )} c stn = 270 pf/{[r gn (k w ) || r rcv (k w )]/24 (k w )} 12-3013.j (f) figure 38. ac equivalent circuit including spare op amp r p z t + C r p v t/r i t/r v s z t/r + C ring a v = C1 a v = 1 vitr C + + C current sense tip + C r t3 r rcv r hb1 r t6 rcvn rcvp r x vgsx vfxin vfr 1/2 t7504 codec r gp +2.4 v C0.400 v/ma a v = 4 l8560 slic vfxip r stp c stp + C z t5 sn agnd r t5x c stn r p z t + C r p v t/r i t/r v s z t/r + C ring a v = C1 a v = 1 vitr C + + C current sense tip r t4 + C r t3 r rcv r hb1 r t6 rcvn rcvp r x vgs x vfxin vfro 1/4 t7504 codec r gn +2.4 v l8560 slic a v = 4 r stn xmt vfxip
lucent technologies inc. 39 data sheet april 2000 l8560 low-power slic with ringing applications (continued) design examples in the preceding examples, use of a first-generation codec is shown. the equations for second- and third- generation codecs are simply subsets of these. there are two examples below. the first shows the simplest circuit, which uses a minimum number of discrete com- ponents to synthesize a real termination impedance. the second example shows the use of the uncommit- ted op amp to synthesize a complex termination. the design has been automated in a dos-based program, available on request. example 1, real termination the following design equations refer to the circuit in figure 37. use these to synthesize real termination impedance. termination impedance: z t = receive gain: transmit gain: hybrid balance: h bal = 20log h bal = 20log to optimize the hybrid balance, the sum of the currents at the vfx input of the codec op amp should be set to 0. the expression for zhb becomes: example 2, complex termination for complex termination, the spare op amp may be used (see figure 38). = 2r p + k(z t5 ) g tx = the hybrid balance equation is the same as in exam- ple 1. example 3, complex termination without spare op amp the gain shaping necessary for a complex termination impedance may be done without using the spare op amp by shaping across the ax amplifier at nodes tg and vtx. this is a recommended approach. v t/r i t/r C ------------ z t 2r p 3200 1 r t3 r gp -------- - r t3 r rcv ----------- - ++ ----------------------------------- + = g rcv v t/r v fr ----------- - = g rcv 8 1 r rcv r t3 ----------- r rcv r gp ----------- - ++ ? ?? 1 z t z t/r -------- - + ? ?? ------------------------------------------------------------------ = g tx v gsx v t/r ---------- - = g tx r x C r t6 --------- 400 z t/r -------- - = r x r hb1 -------------- - g tx C g rcv ? ?? v gsx v fr -------------- - ? ?? r hb1 k w () r x g tx g rcv ------------------- = z t 2r p 3200 1 r t3 r gn --------- r t3 r rcv ----------- - ++ ----------------------------------- z t5 r t4 --------- () + = g rcv 8 1 r rcv r t3 ------------- - r rcv r gn ------------- - ++ ? ?? 1 z t z t/r ---------- + ? ?? ----------------------------------------------------------------------------- = r x r t6 --------- 400 z t/r ---------- z t5 r t4 --------- 1 r t5x z t5 ------------- - r t5x r t3 r g n || r rcv + --------------------------------------------------- - ++ ? ??
40 40 lucent technologies inc. data sheet april 2000 l8560 low-power slic with ringing applications (continued) design examples (continued) complex termination impedance design example using l8560 without spare op amp complex termination is specified in the form: 5-6396(f) to work with this application, convert termination to the form: 5-6398(f) where: r 1 = r 1 + r 2 r 2 = (r 1 + r 2 ) c = c ac interface using first-generation codec r tgp /r tgs /c gs (z tg ): these components give gain shaping to get good gain flatness. these components are a scaled version of the specified complex termina- tion impedance. note for pure (600 w ) resistive terminations, compo- nents r tgs and c gs are not used. resistor r tgp is used and is still 4.32 k w . r x /r t6 : with other components set, the transmit gain (for complex and resistive terminations) r x and r t6 are varied to give specified transmit gain. r t3 /r rcv /r gp : for both complex and resistive termina- tions, the ratio of these resistors set the receive gain. for resistive terminations, the ratio of these resistors set the return loss characteristic. for complex termina- tions, the ratio of these resistors set the low-frequency return loss characteristic. c n /r n1 /r n2 : for complex terminations, these compo- nents provide high-frequency compensation to the return loss characteristic. for resistive terminations, these components are not used and r cvn is connected to ground via a resistor. r hb : sets hybrid balance for all terminations. set z tg gain shaping: z tg = r tgp || r tgs + c gs which is a scaled version of z t/r (the specified termination resistance) in the r 1 || r 2 + c form . r tgp must be 4.32 k w to set slic transconductance to 400 v/a r tgp = 4.32 k w at dc, c tgs and c are open. r tgp = m x r1 where m is the scale factor. m = it can be shown: r tgs = m x r2 and c tgs = r 2 c r 1 r 1 c r 2 r 1 r 2 ------- r 2 r 1 r 2 + --------------------- ? ?? 2 4320 r 1 -------------- c m ------
data sheet april 2000 lucent technologies inc. 41 l8560 low-power slic with ringing applications (continued) design examples (continued) 5-6400.b (f) figure 39. interface circuit using first-generation codec (blocking capacitors not shown) 0.1 m f r tgs v tx r tgp = 4.32 k w t xi v itr r t6 r x r t3 r hb codec output drive amp codec op amp C + 19.2 c n r n1 r n2 r gp r rcv rcvn rcvp Ci t/r 207.36 c g transmit gain transmit gain will be specified as a gain from t/r to pcm, t x (db). since pcm is referenced to 600 w and assumed to be 0 db, and in the case of t/r being refer- enced to some complex impedance other than 600 w resistive, the effects of the impedance transformation must be taken into account. again, specified complex termination impedance at t/r is of the form: 5-6396(f) first, calculate the equivalent resistance of this net- work at the midband frequency of 1000 hz. r eq = using r eq , calculate the desired transmit gain, taking into account the impedance transformation: t x (db) = t x (specified[db]) + 20 log t x (specified[db]) is the specified transmit gain. 600 w is the impedance at the pcm and r eq is the impedance at tip and ring. 20 log represents the power loss/gain due to the impedance transformation. note in the case of a 600 w pure resistive termination at t/r 20 log = 20 log = 0. thus, there is no power loss/gain due to impedance transformation and t x (db) = t x (specified[db]) . finally, convert t x (db) to a ratio, g tx : t x (db) = 20 log g tx the ratio of r x /r t6 is used to set the transmit gain: = g tx ? ? with a quad lucent codec such as t7504: r x < 200 k w r 2 c r 1 2 p f () 2 c 1 2 r 1 r 2 2 r 1 r 2 ++ 12 p f () 2 r 2 2 c 1 2 + ----------------------------------------------------------------------------- ? ?? 2 2 p f r 2 2 c 1 12 p f () 2 r 2 2 c 1 2 + -------------------------------------------------- - ? ?? 2 + 600 r eq ---------- - 600 r eq ---------- - 600 r eq ---------- - 600 600 --------- - r x r t6 ---------- 207.36 19.2 ----------------- - 1 m ---- -
42 42 lucent technologies inc. data sheet april 2000 l8560 low-power slic with ringing applications (continued) design examples (continued) receive gain ratios of r rcv , r t3 , r gp will set both the low-frequency termination and receive gain for the complex case. in the complex case, additional high-frequency compen- sation, via c n , r n1 , and r n2 , is needed for the return loss characteristic. for resistive termination, c n , r n1 , and r n2 are not used and r cvn is tied to ground via a resistor. determine the receive gain, g rcv , taking into account the impedance transformation in a manner similar to transmit gain. r x (db) = r x (specified[db]) + 20 log r x (db) = 20 log g rcv then: g rcv = and low-frequency termination z ter(low) = + 2r p z ter(low) is the specified termination impedance assum- ing low frequency (c or c is open). r p is the series protection resistor. these two equations are best solved using a computer spreadsheet. next, solve for the high-frequency return loss compen- sation circuit, c n , r n1 , and r n2 : c n r n2 = c g r tgp r n1 = r n2 there is an input offset voltage associated with nodes r cvn and r cvp . to minimize the effect of mismatch of this voltage at t/r, the equivalent resistance to ac ground at r cvn should be approximately equal to that at r cvp . refer to figure 40 on page 43 (with dc block- ing capacitors). to meet this requirement, r n2 = r gp || r t3 . hybrid balance set the hybrid cancellation via r hb . r hb = r eq 600 ---------- - 4 1 r rcv r t3 --------------- r rcv r gp --------------- ++ ----------------------------------------------- - 3200 1 r t3 r gp ----------- - r t3 r rcv --------------- ++ -------------------------------------------- 2r p 3200 ------------ - 3200 2r p ------------ - r tgs r tgp ------------- - ? ?? 1 C r x g rcv g tx ------------------------------ -
lucent technologies inc. 43 data sheet april 2000 l8560 low-power slic with ringing applications (continued) design examples (continued) blocking capacitors 5-6401b(f) figure 40. ac interface using first-generation codec (including blocking capacitors) for complex termination impedance if a 5 v only codec such as the lucent t7504 is used, dc blocking capacitors must be added as shown in figure 40. this is because the codec is referenced to 2.5 v and the slic to groundwith the ac coupling, a dc bias at t/r is eliminated and power associated with this bias is not consumed. typically, values of 0.1 f to 0.47 f capacitors are used for dc blocking. the addition of blocking capacitors will cause a shift in the return loss and hybrid balance frequency response toward higher frequencies, degrading the lower-frequency response. the lower the value of the blocking capacitor, the more pronounced the effect is, but the cost of the capacitor is lower. it may be necessary to scale resistor values higher to compensate for the low-frequency response. this effect is best evaluated via simulation. a pspice * model for the l8560 is available. design equation calculations seldom yield standard component values. conversion from the calculated value to standard value may have an effect on the ac parameters. this effect should be evaluated and optimized via simu- lation. * pspice is a registered trademark of microsim corporation. 0.1 m f r tgs v tx r tgp = 4.32 k w t xi v itr r t6 r x r t3 r hb codec output drive amp codec op amp C + 19.2 c n r n1 r n2 r gp r rcv rcvn rcvp Ci t/r 207.36 c gs c b1 2.5 v c b2
data sheet april 2000 l8560 low-power slic with ringing 44 lucent technologies inc. outline diagrams 32-pin plcc dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schemat- ics to assist your design efforts, please contact your lucent technologies sales representative. 5-3813r2 (f) 0.10 seating plane 0.38 min typ 1.27 typ 0.330/0.533 1 430 5 13 21 29 14 20 12.446 0.127 11.430 0.076 pin #1 identifier zone 14.986 0.127 13.970 0.076 3.175/3.556
lucent technologies inc. 45 data sheet april 2000 l8560 low-power slic with ringing outline diagrams (continued) 44-pin plcc dimensions are in millimeters. note: the dimensions in this outline diagram are intended for informational purposes only. for detailed schemat- ics to assist your design efforts, please contact your lucent technologies sales representative. 5-2506r.8(f) 4.57 max 1.27 typ 0.53 max 0.10 seating plane 0.51 min typ 1 640 7 17 29 39 18 28 pin #1 identifier zone 16.66 max 17.65 max 16.66 max 17.65 max
da t a s h eet april 2000 l8560 low-power slic with ringing l u cent t e chnolo g ies inc . res e rves t he r i g ht t o mak e cha n ges t o th e pro d uct(s ) o r info r matio n cont a ined h erei n withou t notice . n o liabilit y i s assu m ed as a r esult o f thei r use or a pplicatio n . no r ights u n der a ny pa t ent acc o mpa n y the s a le of a ny such p rod u ct(s ) or in f orm a tion. co p yrigh t ? 200 0 luce n t t echn o logies i n c. all rights res e rved april 2000 ds00 - 172alc (replaces d s 99-124 a lc) f o r a d d i ti o n a l i n fo r m a t i o n , c o n ta c t y o u r m i c r o e l e c t r o n i c s g r o u p a cc o u n t m a n a ge r o r t h e f o l l o wi n g: i n terne t : http://ww w .lucent.com/micro e-m a il: do c m a ste r @mi c ro . luc e nt.com n . a m e r ic a : m i c r o e l e c t r o n i cs g r o u p, l u c e nt t e c hn o l o g i e s i n c ., 5 5 5 u n i o n b o u l e v a r d , r o o m 3 0 l - 1 5 p - b a , a l l e nt o wn , p a 1 8 1 0 3 1 - 80 0 - 37 2 - 2 4 4 7 , f a x 6 1 0 - 7 1 2 - 4 10 6 ( i n c a n a d a : 1 - 8 0 0 - 5 5 3 - 2 44 8 , f a x 6 1 0 -7 1 2 - 4 1 0 6 ) a s i a p a cif i c : m i c r o e l e c t r o n i cs g r o u p, l u c e nt t e c hn o l o g i e s s i ng a p o r e p t e . l t d., 7 7 s c i e n c e p a r k d r i v e, #0 3 - 1 8 c i nt e c h i i i, s i n g a p o r e 1 1 8 2 56 t el . ( 6 5 ) 77 8 8 83 3 , f a x ( 6 5 ) 7 7 7 74 9 5 c h i n a: m i c r o e l e c t r o n i cs g r o u p, l u c e n t t e c h n o l og i e s ( c h i na ) c o., l td . , a - f 2 , 2 3 / f , za o fo n g u n i v e r s e b u i l d i n g , 1 8 0 0 zh o ng s h an x i r o a d , s h a n g h ai 2 00 2 3 3 p . r. ch i na t e l . ( 8 6 ) 2 1 6 4 4 0 0 4 6 8 , e x t . 3 1 6 , f a x ( 86 ) 21 64 4 0 06 5 2 j a p a n : m i cr o e l e c t r o n i cs g r o u p, l u c e nt t e c hn o l o g i e s j a pa n l t d., 7 - 1 8 , h i g a s h i - got a n d a 2 - c h o m e, s h i n a g aw a - k u , t o k y o 1 4 1, j a p a n t e l . ( 8 1) 3 5 4 21 1 60 0 , f a x ( 8 1 ) 3 5 4 2 1 17 0 0 e u r op e : d at a r e qu e s t s : m ic r o e l e ct r oni c s g r ou p d a t a l i n e : t el . ( 44 ) 70 0 0 5 8 2 3 6 8 , f a x ( 44 ) 1 1 8 9 3 2 8 1 48 t e c h n i c a l in q u i r i e s : g e r ma n y : ( 4 9 ) 89 9 5 0 8 6 0 (munich ) , united kingdom: ( 4 4 ) 1 3 4 4 8 6 5 9 0 0 ( a scot) , f r a n ce: ( 3 3 ) 1 4 0 8 3 6 8 0 0 (p a r i s), s we d e n : ( 4 6) 8 5 9 4 6 07 00 (stockholm), f inl a nd: ( 3 5 8 ) 9 4 3 5 4 2 80 0 ( h e l si n ki ) , i t a l y : ( 3 9 ) 0 2 6 6 0 8 13 1 (m i l a n ) , s p a i n : ( 3 4 ) 1 8 0 7 1 4 4 1 (madrid) ordering information device code description package comcode l u cl8 5 60aau-d low-p o wer slic (dry- b agg e d) 32-pin p l cc 1 07 9 573 7 5 l u cl8 5 60aau-dt lo w - p ower sli c ( t a p e a n d r e el, dry-b a gge d ) 32-pin p l cc 1 07 9 573 8 3 l u cl8 5 60ap-d low-p o wer slic (dry- b agg e d) 44-pin p l cc 107 8 9 11 1 1 l u cl8 5 60ap-dt lo w - p ower sli c ( t a p e a n d r e el, dry-b a gge d ) 44-pin p l cc 1 07 8 9 1 1 2 9 l u cl8 5 60cau-d low-p o wer slic (dry- b agg e d) 32-pin p l cc 1 07 9 533 9 0 l u cl8 5 60cau-dt lo w - p ower sli c ( t a p e a n d r e el, dry-b a gge d ) 32-pin p l cc 1 07 9 534 0 8 l u cl8 5 60dau-d low-p o wer slic (dry- b agg e d) 32-pin p l cc 1 08 1 305 7 6 l u cl8 5 60dau-dt lo w - p ower sli c ( t a p e a n d r e el, dry-b a gge d ) 32-pin p l cc 1 08 1 305 8 4 l u cl8 5 60ep-d low-p o wer slic (dry- b agg e d) 44-pin p l cc 1 08 1 330 0 0 l u cl8 5 60ep-dt lo w - p ower sli c ( t a p e a n d r e el, dry-b a gge d ) 44-pin p l cc 1 08 1 330 1 8 l u cl8 5 60 f au-d low-p o wer slic (dry- b agg e d) 32-pin p l cc 1 08 1 908 8 5 l u cl8 5 60 f au-dt lo w - p ower sli c ( t a p e a n d r e el, dry-b a gge d ) 32-pin p l cc 1 08 1 908 9 3 l u cl8 5 60gp-d low-p o wer slic (dry- b agg e d) 44-pin p l cc 1 08 1 909 3 5 l u cl8 5 60gp-dt lo w - p ower sli c ( t a p e a n d r e el, dry-b a gge d ) 44-pin p l cc 1 08 1 909 4 3

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